The present invention relates to a liquid crystal display, and more particularly to an active matrix liquid crystal display with a reduced number of driver circuits for signal lines whilst obtaining an improved display quality.
In recent years, liquid crystal displays using thin film transistors have been widely used as a display of various electronic devices particularly a note-type personal computer. Reduction in the price of the various electronic devices particularly the note-type personal computer has been required. In order to realize the required reduction in the price of the various electronic devices particularly the note-type personal computer, it is essential to reduce the cost of the driver IC use as a driver circuit for driving the signal lines in the liquid crystal display panel. The reason why the driver IC is expensive is the high cost of the individual driver IC due to its high performance and a large number of the driver ICs to be used. In this circumstance, it was proposed to reduce the number of the driver ICs to be used. In the Japanese laid-open patent publications Nos. 3-38689, 5-26504 and 6-148680, it is disclosed that adjacent two pixels commonly use a signal line extending between the adjacent two pixels so as to reduce by half the signal line driver ICs.
The following descriptions will focus on the technique of reducing by half the number of the driver ICs for the signal lines. FIG. 1 is a block diagram illustrative of a typical and conventional active matrix liquid crystal display. The active matrix liquid crystal display has a liquid crystal display panel 1 for displaying images. A signal line driver circuit 2 is provided for driving signal lines of the liquid crystal display panel 1. A scanning driver circuit 3 is provided for driving scanning lines of the liquid crystal display panel 1. A timing generator circuit 5 is provided which is connected to both the signal line driver circuit 2 and the scanning driver circuit 3 for supply control signals to both the signal line driver circuit 2 and the scanning driver circuit 3 respectively. The timing generator circuit receives a vertical synchronizing signal "Vsync", a horizontal synchronizing signal "Hsync" and a dot clock signals "CLK" and generates various control signals. A data processing circuit 4 is further provided which is connected to the timing generator circuit 5 for fetching control signal. The data processing circuit 4 is also connected to the signal line driver circuit 2 and also adopted to receive data and process the received data for supplying the processed data to the signal line driver circuit 2 as the data interface.
FIG. 2 is a circuit diagram illustrative of connections among scanning lines, signal lines, thin film transistors, pixel electrodes and a common electrode. The scanning lines G1 to Gm are provided which extend in row direction and in parallel to each other. The signal lines S1 to Sn are also provided which extend in column direction vertical to the row direction and in parallel to each other. The scanning lines G1 to Gm and the signal lines S1 to Sn form matrixes. Display pixels are aligned in matrix. The display pixels are connected through thin film transistors, TFT to the signal lines. Gates of the thin film transistors TFT are connected to the scanning lines. Source electrodes of the thin film transistors TFT are also connected to the display pixels. Drain electrodes of the thin film transistors TFT are also connected to the signal lines S1 to Sn. The display pixels and the common electrode form capacitances.
FIG. 3 is a driving timing chart of the conventional active matrix liquid crystal display. Data are inputted into the data processing circuit 4 and the processed signals are then inputted into the signal line driver circuit 2. Notwithstanding, in view of the one horizontal period 1H, data may be considered to be inputted into the signal line driver circuit 2 at almost the same timing as the timing of the data input into the data processing circuit 4. The data for the one horizontal period 1H are sequentially accumulated in the signal line driver circuit 2 until the full accumulation could be achieved for subsequent one time outputs of the data to individual output terminals of the signal line driver circuit 2. When data to the first line are outputted thereto, the scanning line driver circuit 3 outputs the output signal G1 which is capable of turning the thin film transistor ON. After the output of the data to the first line has been completed, the output signal G1 from the scanning line driver circuit 3 is changed into the OFF voltage which is capable of turning the thin film transistor OFF. Concurrently, data for the second line are about to be outputted whereby the output signal G2 from the scanning line driver circuit 3 is changed into the ON voltage which is capable of turning the thin film transistor ON. In synchronous to the output of the line data, the ON voltage is shifted over the scanning lines. In this time, if the common electrode remains constant in voltage level, the ON voltage is about 20 V whilst the OFF voltage is about -7 V. When the scanning line is in ON, the TFT is conductive whereby a potential of the signal line is written into the pixel. Data are sequentially written into the display pixels for individual horizontal lines so that display patterns for one frame are formed in the one vertical period. The polarity of the signal data is inverted for every outputs or every lines. Output of the signal line driver circuit 2 are opposite to each other between adjacent two signal lines for dot inversion. For one time data writing or one line data writing, the adjacent outputs are opposite to each other in polarity, for which reason potential of the common electrode is free from any variation. Images written in the one frame is as illustrated in FIG. 4, fore which reason even if the positive and negative writings are different from each other, then approximate uniformity can be obtained for good display performance.
In order to reduce the cost of the liquid crystal display, it was proposed to reduce by half the number of the signal line drifter ICs. The adjacent two pixels commonly use the signal line and thus the number of the outputs of the signal line driver circuits is reduced by half The size of the circuits is also reduced by half By contrast, the number of the scanning lines is increased by double. The size of the circuit is also double. The scanning line driver circuit is more simple in circuit configuration than the signal line driver circuit, for which reason the scanning line driver circuit is lower in cost than the signal line driver circuit.
FIG. 5 is a circuit diagram illustrative of a second conventional liquid crystal display. The adjacent two pixels commonly use the signal line extending between the adjacent two pixels. The pixel is connected through the thin film transistor into the signal line. For a single horizontal display line, two scanning lines are allocated. The thin film transistors are alternately connected through those gates to the different and adjacent scanning lines.
FIG. 6 is a timing chart of the second conventional liquid crystal display. Data are inputted into the data processing circuits and are divided by the data processing circuits into odd and even data groups A and B so that data divided into the odd and even data groups A and B are output in a half horizontal period. The data processing circuits need line memories. In accordance with the output of the signal line driver circuit, the ON voltage of the thin film transistor is shifted over the scanning lines sequentially. The odd and even data are alternately written. The one time writing time-period is half of the normal one since the odd and even data are sequentially written.
By the way, adjacent two outputs are opposite in polarity to each other. If as illustrated in FIG. 6 the output is inverted in polarity for every times, then the polarity is changed for every two columns as illustrated in FIG. 7. If the negative and positive polarity writings are different from each other, then column stripes appear on the display. In order to settle this problem, it is effective to modify the signal or scanning line driver circuits. For example, all of the outputs from the signal line driver circuits have the same polarity and the polarity is inverted for every two outputs so that the dot inversion display screen illustrated in FIG. 4 can be obtained.
Even if all of the outputs from the signal line driver circuits have the same polarity, then a unidirectional current flows toward the common electrode and a voltage drop is caused whereby the potential of the common electrode is frictional. This provides an influence to the display quality. Also if the output form the signal line driver circuit is inverted for every one output and the ON voltage shift over the scanning line is alternatively carried out, then the two times ON voltage shifts form the dot inversion display as illustrated in FIG. 4 can be obtained. In this case, however, the data processing in correspondence to the scanning, line driving operations is required, for which reason the frame memory is also required. The scanning line driver circuit is not so simple rather complicated. As a result, the cost of the display is increased. Of course, the signal lines are driven in the same polarity, for which reason the above described influences are problem.
On the other hand, in view of the practice, the signal line driving ability and the price of the chip depending upon the chip area, it is important issue whether the polarity inversion may respond only for every one output or for every two or more outputs. Recently developed liquid crystal display has a large scale screen of 12 inches or more and has a high solution XGA or more. This means that the one horizontal period is shorten. This means that the signal writing time period makes large the load of the signal line driver circuit and the resistance and capacitance of the signal line. For example, in case of SVGA, the one horizontal time period is about 27 microseconds. In case of XGA is about 20 microseconds. Notwithstanding, if the number of the signal lines is reduced by half, then it is required to write the data within a quarter. This means the driving ability is sufficient for driving the signal lines.
If in order to drive a large display screen and a high solution display at high quality, the dot inversion driving for the low voltage driver ICs are required. The low power consumption is also required. This means the dynamic range may be set up to the power voltage, for which reason the driver ICs are required so that the adjacent outputs are inverted in polarity and sufficient driving ability is possessed and further the dynamic range takes the power voltage. For that purpose, the amplifier as the output stage is optimally as illustrated in FIGS. 8A and 8B.
In view of the reduction in the cost, it is preferable that the adjacent outputs are opposite in polarity and both outputs are inverted for every one and further the ON voltage of the thin film transistor is shifted over the scanning lines. However, this type of the display panel is hard to carry out the dot inversion driving for the high quality display for the reasons as described above.